Joe's 1000x600x200 steel and aluminium router started

[devmonkey]

So I've just scoped the DDCS. An axis setup as per my machine, 1610 screw, 16x ustepping -> 320 steps/mm, max speed 10000mm/min.

As expected step frequency is ~53kHz, half period of 9.375us. Nyquist/Shannon tell us that this needs to be sampled at a minimum of 2f, i.e. 106kHz for perfect reconstruction. Puts an upper bound on my mirror code latency of ~9us, so to be safe say 5us. This is 80 cpu cycles, will it fit?? Should do, got to wire it in and test.

DDCS defaults set dir 7000ns (7us) ahead of step therefore code running at 5us will always see this. EM806 only requires 2.5us but configuring DDCS to deliver this will risk breaking the contract woth EM806.