Well lets think this through...

Whats the slowest meaningful step rate, 1 step/second? how long after the last step do we want to wait, 10 seconds?

So every time there is a clock pulse, reload an 'n' second counter. when the counter reaches 0 start a PWM output with a frequency of 100Hz say, and a mark/space ratio controlled from 2 dip switches giving 100 (off), 75, 50 and 25 settings

Use a couple more DIP switches to set the initial delay 'n', say 20, 10, 5, 2 seconds.

Pseudocode:

Interrupt routines:
If INT0 (external)
read delay value
reset main counter to delay value
set PWM output high (open collector)
reset INT0
return
If INT1 (main counter reached 0)
read PWM value
initialise PWN registers
start PWM running
reset INT1
return
Main program:
set PWM frequency
set PWM output high
configure counter clock divider
configure INT0 on external trailing edge
configure INT1 on counter timeout
read delay value
reset main counter to delay value
enable INT0
enable INT1
halt
obviously, depending on the chip used you may have to synthesise the PWM function with counters and a lookup table to determine the correct counts for each DIP setting.