Soft Start Inrush Current Limiter- PCB design

[TStar]

Thanks for the feedback, Rod's design produces a much shorter delay, he says the optimum is around 100ms, just 5 cycles. With the 100K variable resistor my version should produce a range of 0-500ms. The combined resistance of the parallel resistor bank is 50 Ohms. This should only protect against initial inrush, and hopefully won't cause much heating of the resistors. It won't do anything about the problem of remanance though. I guess a solution to that might be a switching circuit which is synchronized to the AC? This would involve zero cross detection. I know there are relays out there which have built-in zero cross detection. It still wouldn't solve the polarity though, it could start half a wave out of sync.