Thread: Cheap Idea for a DRO
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17-05-2010 #11
ISTR you can fit one or more PICs as required.
I'm getting to understand your assembly code
From memory, the Txsyn timing is a simple grab a slot when ready affair with a different delay based on chip position to help prevent collisions.
(i.e. if Txsyn = hi, delay X.Y,Z or W recheck Txsyn if hi, pull txsyn low and transmit)
Is the vernier being switched into fast mode correctly? Different makes/types of scale have different clk/data line switching sequences so some don't work with out mod'ing the code
Are you powering the scales from the interface or the on-board cell? (I replaced the cells with a ~1uF SM cap) What voltage are you ghetting across the PSU red-led?
The serial port is running at 115,200 baud, so screening and good earthing is advisable. And, it derives its -Ve from the PC so, just check that's working OK.
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