Thread: Ready Steady Eddy
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19-11-2013 #11
Thanks for taking the time to reply Jonathan. Very helpful. I was also having hard time understanding/visualising the "active low" part of the puzzle.
This also helped me understand:-
"If the input signal is high there will flow current through R2 and the transistor's base-emitter junction (base, not gate). This current will be amplified, and the collector current through R1 will cause a voltage drop so that the output will be low. Input high, output low.
If the input signal is low there won't be any base current, and no collector current. No current through R1 means no voltage drop, so that the output will be at +V. Input low, output high."
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